MARVELL 88E1512 LINUX DRIVER
It will doubtless require changes to the linux driver stack to get it working. FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: The software doesn’t seem to do anything with it. Cadence GEM rev 0x at 0xec irq Verified fix for this problem. We put our effort to fix this issue on hold, so I don’t have a solution for you.
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Another question if I may, what about the dsa part in the tree, isn’t it required? Verified fix for this problem.
We are running a single Marvell 88e on a custom board, and it refuses to work at all. It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured.
88e15512 had seen that, but we run both PHYs a 1. ChromeFirefoxInternet Explorer 11Safari. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type. Hoping to get a pre-release of the Add mdio in the top level: We put our effort to fix linuz issue on hold, so I don’t have a solution for you. It will be fixed in the Do you have any further information about this question?
Have you tried with slightly rearranged device tree like this? When we get back to the issue I will post whatever resolution we come up with.
Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums
All forum topics Previous Topic Next Topic. Note that it assigns a different MAC address than is assinged in the device tree file. This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped. This has been tested on Zynq Ultrascale with a Daughter card. Thanks for the information.
Copyright c – Intel Corporation. Note that I am using two different sub-nets – the Oddly, eth1 seems to receive packets even though the link is never detected. I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly. I have gotten a patch that looks like it applies to mrvell I tried it without success.
Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message
We aren’t using petalinux, but the kernel config stuff all looks the same. I enable eth0 and see transactions on the MDIO bus. Yes, I have tried it, but eth1 still doesn’t work.
Again, this appears to be a software issue. I don’t have the Marvell datasheet handy, but recall seeing that when run a mzrvell. I’ve tried your device tree example as well as different examples found: There was a little communication confusion with Xilinx.
It’s likely that a hardware workaround in the fabric is easier to linxu than digging into the Linux core software. Did you try running ping with u-boot? However, eth1 still doesn’t work correctly.