The CCFL circuit of claim 5 , wherein the snubber circuit includes first and second diodes, a capacitor, and a resistor, an input terminal of the first diode being connected to an end of the first primary winding, an input terminal of the second diode being connected to the end of the second primary winding, and output terminals of the first and second diodes being connected to a node, the resistor and the capacitor being connected in parallel between the node and the battery. In many applications, a key design goal is to minimize variations in power delivered to a load as the supply voltage varies. In a balanced circuit, the voltage at the connection of the two secondary windings will, ideally, be zero. A CCFL-determined secondary voltage is generally considered advantageous because it eliminates the ballasting capacitor. This logic zero signal propagates through the subsequent logic gates as the NORM signal. The invention relates to driving a CCFL cold cathode fluorescent lamp with a high voltage sine wave to produce an efficient and cost effective light source. Low-power single CMOS timer.

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US20050093476A1 – Direct drive CCFL circuit with controlled start-up mode – Google Patents

Method and apparatus providing a multi-function terminal for a power supply controller. Frequency modulated ballast with loosely coupled transformer for parallel gas discharge lamp control.

Therefore, a need arises for a method of increasing the usable life from a CCFL as well as improving cold start operation while using a direct drive CCFL circuit. Opposite ends of a secondary winding of transformer T 3 are connected to ground and an input terminal of the Pmoe. In one embodiment, the battery voltage VBATT can provide V typical for 3 lithium ion cells provided in a notebook computer application. Error amplifier is configured to receive a reference voltage VR 3 and the signal at the source of NMOS transistor However, if the input voltage is greater than the predetermined intermediate voltage but less than a predetermined high voltage, then the frequency can be held at its current value.


An oscillator circuit generates a user-programmable operating frequency with an external capacitor and a timing resistor. The snubbing circuit can include first and second diodes, a capacitor, and a resistor. In contrast, side of the primary coil connected to NMOS transistor is driven to twice the battery voltage.

NMOS and PMOS Short-Channel devices

In other embodiments, pins OVPH and OVPL could be driven from different locations on the resistor divider strings including resistors,and The means for combining can include a third resistor coupled between a high voltage source and an anode of the first diode, a fourth resistor coupled between the high voltage source and an anode of the second diode, a third diode having an anode connected to the anode of the first diode and a cathode connected to the means for comparing, and cvfl fourth diode having an anode connected to the anode of the second diode and a cathode connected to the means for comparing.

Further note that the ramping signal generated at nodei.

Integrated circuit including a switching regulator design for power over Ethernet devices. The system according to claim 12, characterized in that, further comprising a feedback loop, it is only for determining a first current through the CCFL.

In the snubbing circuit, the capacitor, resistor, and diodes are configured to maintain a nominal voltage at the common node. In direct drive CCFL circuitthe sources of n-type transistors and are coupled to ground whereas their drains are connected to opposite ends of the primary winding of a transformer Resistor divider must be sized so that under normal operating conditions the rectified voltage at the output of diode is less than a predetermined threshold of a comparator at the Pjos node of the control IC At this point, PMOS transistor turns on again, thereby allowing current to ramp up in side of the primary winding.


Protecting a cold cathode fluorescent lamp from a large transient current when voltage supply transitions from a low to a high voltage. The brightness may also be controlled by using a variable resistor in place of resistor and The method of claim 19wherein dividing the voltage includes sizing a resistor divider so that: Trace in FIGS.

However, the current decreases very quickly at first then ramps down to zero at a rate that is slower than the current ramped up. Of importance, the resistive and capacitive components of circuit are isolated from the high voltage terminal of CCFL tube i. However, after the gas is ionized, the impedance drops and current starts to flow in the CCFL tube.

CMOS Input Buffer with PMOS and NMOS buffers – YouSpice

The current flowing through resistors and can be sensed at node via line at pin CSDET. In addition, the transformer in the does not require any specific gap-less arrangement. However, if either of the drains of the first and second NMOS transistors have a voltage above that nominal voltage, then the first and second diodes forward bias and allow the ringing energy to charge the capacitor.

Note that the embodiment of FIG.

CNA – Method and system for driving CCFL – Google Patents

The third control block adjusts the brightness by turning the lamp on and off at varying duty cycles. A method implemented in a transformer, said transformer having an intermediate region, a first end and a second end, said method comprising: These applications include backlighting for many consumer products including, for example, notebook computers, flat panel displays, and personal digital assistants PDAs.

White LED power supply for large display backlight. Start display at page:.